1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a defect acceleration test by applying a voltage stress (also referred to as xe2x80x9ca burn-in testxe2x80x9d hereinafter) in a semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading.
2. Description of the Background Art
To speed up data reading and writing operations, it is known to arrange data bus pairs formed with complementary data buses independently for data writing and data reading, respectively.
FIG. 5 is a circuit diagram showing a structure of conventional semiconductor memory device independently including a read data bus pair for data reading and a write data bus pair for data writing.
Referring to FIG. 5, conventional semiconductor memory device 2 includes at least one memory block MB having a plurality of memory cells MCs arranged in rows and columns. In each memory block MB, a plurality of word lines WLs are arranged corresponding to respective memory cell rows, and a plurality of bit line pairs BLPs are arranged corresponding to respective memory cell columns. Each bit line pair BLP has complementary bit lines BIT and /BIT. A structure of kth (k is a natural number) memory block MBk is representatively shown in FIG. 5. In the memory block MBk, word lines WLk1-WLkm are arranged corresponding to respective m (m is a natural number) memory cell rows, and bit line pairs BLPk1-BLPkn are arranged corresponding to respective n (n is a natural number) memory cell columns. A bit line pair BLPk1 is, for example, formed with complementary bit lines BITk1 and /BITk1, and a bit line pair BLPkn is formed with complementary bit lines BITkn and /BITkn.
Semiconductor memory device 2 further includes a write data bus pair LWDBP and a read data bus pair LRDBP provided corresponding to each memory block MB, and a global write data bus pair GWDBP and a global read data bus pair GRDBP provided to a plurality of memory blocks MBs in common. A write data bus pair LWDBPk and a read data bus pair LRDBPk used to data reading and data writing for the memory block MBk are representatively shown in FIG. 5. The write data bus pair LWDBPk is formed with complementary write data buses LWDBk and /LWDBk, and the read data bus pair LRDBPk is formed with complementary read data buses LRDBk and /LRDBk. Similarly, the global write data bus pair GWDBP is formed with complementary global write data buses GWDB and /GWDB, and the global read data bus pair GRDBP is formed with complementary read data buses GRDB and /GRDB.
Semiconductor memory device 2 further includes a plurality of bit line precharge and equalize circuits 10, a plurality of read selection gates 20, a plurality of write selection gates 30, a write control circuit 40, a sense amplifier circuit 50, a read data bus drive circuit 60, a read data bus precharge and equalize circuit 70, a global read data bus precharge and equalize circuit 80, and control circuits 500, 510.
Bit line precharge and equalize circuit 10 is provided corresponding to each memory cell column, and is activated in response to a block activation signal BACTk. More specifically, each bit line precharge and equalize circuit 10 isolates each of the complementary bit lines BIT and /BIT forming the corresponding bit line pair BLP from a bit line precharge voltage Vbp when the corresponding memory block MBk is selected to activate the block activation signal BACTk (to the H level) and a corresponding column selection signal Y1 is also activated (to the H level). In the other periods, it electrically couples each of the corresponding bit lines BITk1 and /BITk1 to the bit line precharge voltage Vbp for precharging.
Read selection gate 20 is provided corresponding to each memory cell column, and is activated in response to a block read activation signal RBACTk. When activated, read selection gate 20 connects the bit line pair BLP of the corresponding memory cell column to the read data bus pair LRDBPk in response to the corresponding one of the column selection signals Y1-Yn. When inactivated, each read selection gate 20 disconnects the bit line pair BLP of the corresponding memory cell column from the read data bus pair LRDBPk, regardless of the corresponding column selection signal.
Write selection gate 30 is provided corresponding to each memory cell column, and is activated in response to a block write activation signal WBACTk. When activated, write selection gate 30 connects the bit line pair BLP of the corresponding memory cell column to the write data bus pair LWDBPk in response to the corresponding one of the column selection signals Y1-Yn. When inactivated, each write selection gate 30 disconnects the bit line pair BLP of the corresponding memory cell column from the write data bus pair LWDBPk, regardless of the corresponding column selection signal.
Write control circuit 40 is activated in response to the block write activation signal WBACTk. When activated, it sets the voltages of the write data buses LWDB and /LWDB corresponding to the voltages of the global write data buses GWDB and /GWDB which transfer the write data.
Sense amplifier circuit 50 is activated in response to a block sense enable signal BSSEk. When activated, it amplifies a voltage difference between the read data buses LRDBk and LRDBk.
Read data bus drive circuit 60 drives the voltages of the global read data buses GRDB and /GRDB such that, the voltage difference corresponding to that between the read data buses LRDBk and /LRDBk is generated between the global read data buses GRDB and /GRDB.
Read data bus precharge and equalize circuit 70 is provided corresponding to the read data bus pair LRDBPk, and is activated in response to a local precharge signal /LDPCHk. When activated, read data bus precharge and equalize circuit 70 sets each of the corresponding read data buses LRDBk and /LRDBk to the precharge voltage (for example, a power supply voltage Vcc). When inactivated, it isolates each of the corresponding read data buses LRDBk and /LRDBk from the precharge voltage.
Though bit line precharge and equalize circuit 10, the plurality of read selection gates 20, the plurality of write selection gates 30, write control circuit 40, sense amplifier circuit 50, read data bus drive circuit 60, and read data bus precharge and equalize circuit 70 corresponding to the memory block MBk are representatively shown in FIG. 5, such circuit group is similarly provided to each memory block.
Global read data bus precharge and equalize circuit 80 is activated in response to a global precharge signal /GDPCH. When activated, it sets each of the global read data buses GRDB and /GRDB to the precharge voltage (for example, the power supply voltage Vcc). When inactivated, it isolates each of the global read data buses GRDB and /GRDB from the precharge voltage.
The structure of the control circuit will be described in the following. Hereinafter, a high voltage state (the high level) and a low voltage state (the low level) of each signal line, signal or data having binary levels will simply be referred to as xe2x80x9cthe H levelxe2x80x9d and xe2x80x9cthe L levelxe2x80x9d.
Control circuit 500 generates a read activation signal RACT and a sense enable signal SE which are activated in data reading. Control circuit 500 includes an internal clock signal intCLK, a logic gate 502 outputting an NAND logical operation result with a read cycle signal RE which is set to the H level in data reading, an inverter 504 inverting the output of logic gate 502, and a delay circuit 506 delaying the output of inverter 504. The output of inverter 504 is provided as the read activation signal RACT to control circuit 510. The output of delay circuit 506 is provided as the sense enable signal SE to control circuit 510.
Control circuit 510 controls the activation of bit line precharge and equalize circuit 10, read selection gate 20, write selection gate 30, write control circuit 40, sense amplifier circuit 50, read data bus precharge and equalize circuit 70, and global read data bus precharge and equalize circuit 80. In FIG. 5, a structure to control the activation of such circuit group corresponding to the memory block MBk is representatively shown for control circuit 510.
Control circuit 510 includes a logic gate 512 outputting an NAND logical operation result of a block selection signal Zk which is activated to the H level when the memory block MBk is selected and a chip activation signal ACT, and an inverter 514 inverting the output of logic gate 512 and generating the block activation signal BACTk. Control circuit 510 further includes a logic gate 522 outputting an NAND logical operation result of a write activation signal WACT and the block selection signal Zk, and an inverter 524 inverting the output of logic gate 522 and outputting the block write activation signal WBACTk.
The block activation signal BACTk is activated in a synchronized timing with the chip activation signal ACT when the corresponding memory block MBk is selected in each of data writing (the write mode) and data reading (the read mode). The block write activation signal WBACTk is activated in a synchronized timing with the write activation signal WACT when the corresponding memory block MBk is selected in data writing (the write mode).
The block activation signal BACTk is also used as the activation signal of the plurality of bit line precharge and equalize circuits 10 provided corresponding to the memory block MBk. More specifically, bit line precharge and equalize circuit 10 is activated when the corresponding block activation signal BACTk is inactive, and is inactivated according to the column selection result when the corresponding block activation signal BACTk is active. Similarly, the block write activation signal WBACTk is also used as the activation signal of the plurality of write selection gates 30 and write control circuit 40 provided for the memory block MBk. Write selection gate 30 and write control circuit 40 are activated and inactivated when the corresponding block write activation signal WBACTk is active and inactive, respectively.
Control circuit 510 further includes an inverter 530 inverting the sense enable signal SE from control circuit 500, a logic gate 532 for outputting an OR logical operation result of the inverted signal of the output of inverter 530 and the read activation signal RACT, an inverter 534 for further inverting the output of inverter 530, and a logic gate 536 outputting an NAND logical operation result of the output of inverter 530, the block selection signal Zk and the read activation signal RACT. Control circuit 510 further includes an inverter 538 inverting the output of logic gate 536, a logic gate 540 outputting an NAND logical operation result of the block selection signal Zk and the output of logic gate 532, an inverter 542 inverting the output of logic gate 540, a logic gate 544 outputting an NAND logical operation result of the block selection signal Zk and the output of inverter 534, an inverter 546 inverting the output of logic gate 544, and an inverter 548 inverting the output of inverter 530.
Inverter 538 outputs the block read activation signal RBACTk. Inverter 542 generates the local precharge signal /LDPCHk. Inverter 546 outputs the block sense enable signal BSSEk. Inverter 548 generates the global precharge signal /GDPCH.
FIG. 6 shows operation waveforms related to a setting of the control signal group generated by control circuits 500, 510 in data writing (the write mode).
Referring to FIG. 6, the internal clock signal intCLK is generated in synchronization with the clock signal CLK of a prescribed frequency provided to semiconductor memory device 2 from the outside. Internal operation of semiconductor memory device 2 is performed in synchronization with the chip activation signal ACT synchronized with the internal clock signal intCLK. A mode control signal /W is set to the L level in data writing (the write mode), and is set to the H level in data reading (the read mode). The read cycle signal RE is, as the mode control signal /W, activated to the H level in the clock cycle of the read mode, and is inactivated to the L level in the other periods.
An address signal ADD including a row address and a column address is input in synchronization with a rising edge of the clock signal CLK. In FIG. 5, the row address is fixed and the column address is given consecutively.
The word line selected according to the row address (WLk1 in FIG. 5) is activated to the H level in a synchronized timing with the internal clock signal intCLK. The column selection signals selected according to the column address (Y1 and Yn in FIG. 5) are activated to the H level in clock cycles C1 and C2, respectively.
The write activation signal WACT is activated in a synchronized timing with the internal clock signal intCLK in data writing (the write mode), while maintaining the inactive state (the L level) in data reading (the read mode). In contrast, the read activation signal RACT is activated in a synchronized timing with the internal clock signal intCLK in data reading (the read mode), while maintaining the inactive state (the L level) in data writing (the write mode).
The sense enable signal SE is fixed to the inactive state (the L level) in data writing (the write mode). In response to this, the block sense enable signal BSSEk and the block read activation signal RBACTk are fixed to the inactive state (the L level), while the global precharge signal /GDPCH is fixed to the active state (the L level).
In the active period (the H level) of the sense enable signal SE, the local precharge signal /LDPCHk is inactivated to the H level when the corresponding memory block MBk is selected, and is activated to the L level in the other periods including the write mode.
In a clock cycle where the memory block MBk is selected and the block selection signal Zk is activated to the H level, the block activation signal BACTk is activated in a synchronized timing with the chip activation signal ACT. In the write mode, the corresponding block write activation signal WBACTk is also activated in a synchronized timing with the chip activation signal ACT. On the other hand, the block read activation signal RBACTk and the block sense enable signal BSSEk are inactivated to the L level in the write mode even in the selected memory block MBk, as described above.
In the inactive period (the L level) of the block activation signal BACTk, bit line precharge and equalize circuit 10 precharges each of the bit lines BIT and /BIT arranged in the memory block MBk to the bit line precharge voltage Vbp. On the other hand, in the active period (the H level) of the block activation signal BACTk, bit line precharge and equalize circuit 10 is inactivated in response to the column selection signals Y1-Yn and electrically isolates each of the corresponding bit lines BIT and /BIT from the bit line precharge voltage Vbp.
In data writing (the write mode), since each of the plurality of read selection gates 20 is inactivated in each memory block, each of the bit lines BIT and /BIT is not connected to the read data buses LRDB and /LRDB. In addition, since read data bus precharge and equalize circuit 70 and global read data bus precharge and equalize circuit 80 are activated while sense amplifier circuit 50 is inactivated, each of the read data buses LRDBk and /LRDBk and the global read data buses GRDB and /GRDB is precharged to the power supply voltage Vcc. Furthermore, the complementary global write data buses GWDB and /GWDB are set to one and the other of the H level (for example, the power supply voltage Vcc) and the L level (for example, the ground voltage Vss) respectively, corresponding to the write data.
In data writing (the write mode), activated write control circuit 40 in the selected memory block (for example, the memory block MBk) sets the voltage of the corresponding complementary write data buses (for example, the LRDBk and /LRDBk) to one and the other of the H level and the L level respectively, corresponding to the voltages of the global write data buses GWDB and /GWDB. Furthermore, each write selection gate 30 is activated, and the bit lines BIT and /BIT of the memory cell column with the corresponding column selection signals (Y1-Yn) activated are electrically coupled to the write data buses LWDBk and /LWDBk, respectively.
Consequently, the write data buses LWDBk and /LWDBk of the selected memory block are respectively set to one and the other of the H level and the L level by write control circuit 40. In addition, the voltages of the write data buses LWDBk and /LWDBk are transferred to the complementary bit lines of the selected memory cell column (for example, BITk1 and /BITk1 in the clock cycle C1) respectively by write selection gate 30. The voltages of the complementary bit lines of the selected memory cell column are further transferred to the selected memory cell with the corresponding word line (for example, WLk1) activated.
It is to be noted that, though not shown in the drawing, the mode control signal /W is activated to the H level and correspondingly, the read cycle signal RE is set to the H level in the read mode. In response to this, while the write activation signal WACT is fixed to the L level, the read activation signal RACT is activated in the synchronized timing with the chip activation signal ACT. Furthermore, the local precharge signal /LDPCH and the global precharge signal /GDPCH is inactivated to the H level, and the block write activation signal WBACTk is also inactivated to the L level. In contrast, the block read activation signal RBACTk is activated in the synchronized timing with the chip activation signal ACT. In addition, the block sense enable signal BSSEk is set to the H level when the memory block MBk is selected.
Accordingly, in data reading (the read mode), the memory cell group with corresponding word line activated is connected to the corresponding complementary bit lines BIT and /BIT, so that the voltage difference of the polarity corresponding to the stored data of the selected memory cell is generated between the bit lines BIT and /BIT. Because each read selection gate 20 is activated in the read mode, the complementary bit lines BIT and /BIT with corresponding column selection signals (Y1-Yn) activated are electrically coupled to the read data buses LRDBk and /LRDBk, respectively. Furthermore, because read data bus precharge and equalize circuit 70 and global read data bus precharge and equalize circuit 80 are inactivated while sense amplifier circuit 50 is activated, the voltage difference generated between the bit lines BIT and /BIT is amplified and transferred to the read data buses LRDBk and /LRDBk as well as the global read data buses GRDB and /GRDB. As a result, each of the read data buses LRDBk and /LRDBk, and each of the global read data buses GRDB and /GRDB are set to one and the other of the H level (for example, the power supply voltage Vcc) and the L level (for example, the ground voltage Vss) respectively, corresponding to the read data.
Thus, by providing the dedicated data bus groups for data reading and data writing respectively, the precharge of the data bus group for data reading can be performed in the data writing operation. With this, the data reading cycle can be shortened so that the operation of the entire semiconductor memory device can be fastened.
Meanwhile, a defect acceleration test (a burn-in test), to screen a chip by accelerating a potential early defect must be performed in a semiconductor memory device to ensure the operational responsibility. During the burn-in test, such potential defect is revealed generally by applying a high temperature or a high voltage (high electric field) stress to a completely manufactured wafer (chip). For semiconductor memory devices of larger capacity or larger scale, reduction of the needed test time per chip by effectively performing such burn-in test is considered to be important in the aspect of cost reduction.
In the structure of the conventional semiconductor memory device 2 shown in FIG. 5, the burn-in test must be performed while the above-mentioned write mode is set in order to apply an equal stress to each memory cell MC. In practice, the burn-in test is performed after parallel activation of two or more of column selection signals Y1-Yn and selective parallel activation of two or more of word lines WLs besides setting of the write mode.
In the conventional structure wherein the common operations in the write mode and the read mode are performed for the normal operation and the burn-in test, however, the voltage stress cannot be applied to the data bus group of the data reading system, that is, the read data bus pair LRDBP and the global read data bus pair GRDBP. Therefore, the burn-in test must be performed again after switching the operation mode from the write mode to the read mode in order to reveal the early defect of the data bus of the data reading system. This leads to a longer time per chip needed for performing the burn-in test.
An object of the present invention is to perform a burn-in test effectively in a short time in a semiconductor memory device having a structure provided with dedicated data bus groups corresponding to data reading and data writing, respectively.
In summary, the present invention is directed to a semiconductor memory device including a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a write data bus pair, a write control circuit, a plurality of write selection gates, a read data bus pair, a plurality of read selection gates, a sense amplifier circuit, and a precharge and equalize circuit control circuit. Each of the plurality of memory cells stores data. The plurality of word lines are provided corresponding to respective memory cell rows. The plurality of bit line pairs are provided corresponding to respective memory cell columns, and each is formed with complementary first and second bit lines. The write data bus pair is formed with complementary first and second write data buses. When activated, the write control circuit sets the first and second write data buses to one and the other of the first and second voltages respectively, corresponding to write data. The plurality of write selection gates are provided corresponding to respective memory cell columns, and each connects corresponding ones of the first and second bit lines to the first and second write data buses respectively according to a column select result, when activated. The read data bus pair is formed with complementary first and second read data buses. The plurality of read selection gates are provided corresponding to respective memory cell columns, and each connects corresponding ones of the first and second bit lines to the first and second read data buses respectively according to the column select result, when activated. The sense amplifier circuit amplifies a voltage difference between the first and second read data buses, when activated. The precharge and equalize circuit sets each of the first and second read data buses to a prescribed voltage, when activated. The control circuit controls activation of the write control circuit, the plurality of write selection gates, the plurality of read selection gates, the sense amplifier circuit, and the precharge and equalize circuit. The control circuit activates the write control circuit, the plurality of write selection gates, the plurality of read selection gates, and the sense amplifier circuit and deactivates the precharge and equalize circuit, during a test different from a normal operation.
The test preferably corresponds to a burn-in test to reveal a potential defect by applying a voltage stress, and during the test, at least one or a plurality of the memory cell rows and at least one or a plurality of the memory cell columns are selected at one time.
Therefore, a primary advantage of the present invention is that, a voltage difference can be applied between complementary data buses concurrently to both of the read data bus pair for data reading and the write data bus pair for data writing during the test corresponding to the burn-in test. Thus, a voltage stress can be applied between these complementary data buses concurrently without switching the modes in this test. As a result, the burn-in test to reveal an early potential defect by applying a voltage stress can be performed effectively in a short time.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.